The ease with which an integrated electronic circuit is tested is one of the most important concerns in designing such electronic systems. In order to maximize the speed in which a system may be constructed and thereby reduce the cost of the system, systems must be designed so that they may be quickly and efficiently tested. Systems that require long time periods for testing have correspondingly lower throughput and thereby higher cost. Memory circuits provide one of the most important components of integrated electronic systems. The large amounts of memory which are present in modern electronic systems create a proportionally large problem for testing such devices. Each location within the memory system must be addressed to ensure that the address-decoding logic and the conducting path leading to each location are properly functioning.
A particular problem arises when the memory circuit to be tested is a non-volatile programmable memory circuit. Such circuits are very useful in integrated systems because they can have data programmed into them and written from them, but do not require the data refreshing operations which are common with many random access memory systems which use capacitive storage elements. Additionally, non-volatile memory systems have the ability to maintain the integrity of stored data when power is removed from the system. The drawback to many of such non-volatile systems is that the time required to write data to the systems is relatively large. Accordingly, the process of testing the address-decoding logic is considerably slowed by this programming time.
Accordingly, a need has arisen for a memory testing method and system which allows for the efficient and rapid testing of the address-decoding logic present within a memory system that is not slowed by the relatively long programming times required for some memory systems.